RISC-V (pronounced "risk-five": 1 ) is an open standard instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. The project began in 2010 at the University of California, Berkeley, later transferred to the RISC-V Foundation, and on to RISC-V International, a Swiss non-profit entity. Like several other RISC ISA, including Amber (ARMv2), OpenPOWER, OpenSPARC / LEON, and OpenRISC, RISC-V is offered under royalty-free open-source licenses. The documents defining the RISC-V instruction set architecture (ISA) are offered under the BSD License.
Mainline support for RISC-V ISA was added to the Linux 5.17 kernel, in 2022, along with its toolchain. In July 2023, RISC-V, in its 64-bit variant called riscv64, was included as an official architecture of Linux distribution Debian, in its unstable version. The goal of this project was "to have Debian ready to install and run on systems implementing a variant of the RISC-V ISA."
RISC-V International members, like SiFive, Andes Technology, Alibaba's Damo Academy, Raspberry Pi, or Akeana, are offering or have announced commercial Systems On a Chip (SoC) that incorporate one or more RISC-V compatible CPU cores.